亚洲 欧美 图片 自拍 视频

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          VGA synchronous display in LED large screen system application design

          The display screen is divided into synchronous and asynchronous from the communication control mode. The synchronous control mode is real-time communication between the upper computer and the screen. The asynchronous control mode is independent operation between the upper computer and the screen, but the upper computer needs to edit the display information and send it to the display body. This paper presents a design based on synchronous display of the upper computer information display.

          First, the overall design of the system

          The system hardware is divided into three parts. Firstly, the real-time extraction circuit of the display card information is used to extract the VGA monochrome digital video signal, pixel clock, line synchronization and frame synchronization from the graphics card in real time. After processing, it is transmitted by the output medium; the second part is the CRT video signal to the LED display. a signal conversion circuit that selects, stores, reads, distributes, and converts the image signal transmitted by the transmission medium into a display signal corresponding to the LED dot matrix screen; the third part is an LED driver board that receives the converted image The LED displays the signal and assigns it to the pixel corresponding to the LED dot matrix screen to drive the LED display.

          Second, the graphics card display information real-time extraction circuit

          In VGA mode, when displaying a certain color on the VGA, the video memory first outputs a color number, which is actually used to select the palette register, and the selected palette register is generated again. An eight-bit index address is used to select the digital-to-analog converter (DAC color register). There are 256 DAC color registers, each of which consists of 18 bits. When a color register is selected, 18 digital signals are simultaneously output. Perform analog-to-digital conversion, convert to analog red, green, and blue signals, send analog monitors, and scan graphics cards.

          When the VGA is operating in display mode 18, ie, sixteen-color mode, the lower four bits of the eight-bit index address output from the palette register (from P0 to P3) are actually the digital video signals blue, green, red, and luminance. Signal, we can use this feature of VGA to directly extract monochrome digital video signals. In the actual circuit, this function is implemented by the graphics card core feature socket. Among them, P0 to P7 are eight-bit index addresses, and 17-pin, 21-pin, and 23-pin are respectively pixel clock, line synchronization, and field synchronization. On the one hand, the feature socket sends these signals to the color register anti-analog monitor, and on the other hand, it can be externally output. Therefore, we directly extract a monochromatic video signal from the 26-core feature socket of the graphics card, after eight-bit serial conversion and conversion. After long-distance transmission, the pixel clock, field sync signal, and line sync signal are extracted for later signal conversion and display. The eight-bit serial/parallel conversion is based on two reasons: First, because in VGA graphics mode, one pixel consists of eight bits, eight-bit parallel output realizes one pixel and one pixel transmission; the other is eight-bit serial/parallel conversion. Reduced data transfer rate for long-term transmission.

          The VGA scan timing is different from the LED screen scan timing. Therefore, the VGA video signal must be converted into a display signal corresponding to the LED large screen, mainly through two SRAMs.

          Read and write (SRAM1 and SRAM2) are completed. The two SRAMs are alternately in the read/write state. Suppose that in a certain field, SRAM1 is in the write state and SRAM2 is in the read state. At this time, the write signal of SRAM1 is valid, the read signal is invalid, and the write address generated by the write address generator is Sinput input SRAM1, so that the digital video signal is written to SRAM1; for SRAM2, the write signal is invalid, the read signal is valid, and at the same time, the strobe read address is input to SRAM2, thereby reading the data written in the previous field of SRAM2, For distribution, transmission and display.

          (A) the choice of VGA video signal

          The resolution of VGA video is different from that of LED large screen. In this system, the resolution of the LED large screen we achieved is 256?—128, and when the VGA works in 18 mode, the resolution is 640?—480, so the LED screen The entire video image cannot be displayed in its entirety, but only a portion of it can be selected for simultaneous display. The selection of the VGA video image is done by writing the address generator and the read address generator. The write address generator generates a write control signal while generating the write address. The control signal is valid during the selected row in one frame, and the rest of the time is invalid, so that only the data of the selected row is written into the SRAM, and the line is completed. The same reason, the read address generator generates a read control signal while generating the read address, which controls the read shift signal to be valid only during the selected column, that is, only shifts the data of the selected column, thereby completing The choice of VGA video signal column.

          (2) Reading and distribution of SRAM data

          The data stored in the SRAM needs to be read and distributed in a certain order so that it corresponds to the LED large screen. Here, we use the partition circuit method, that is, the entire LED large screen is divided by multiples of 16 and the LED large screen has 256. Line, so it is divided into sixteen partitions. The readout allocation of data is performed in the following order: first, the first pixel of the first row of the first partition, then the first pixel of the first row of the second partition, ... the first pixel of the first row of the sixteenth partition Next, the second pixel of the first row of the first partition... In this order, the read data is output through the eight-bit shift register and serialized, so that the data of the corresponding positions of the sixteen partitions are simultaneously transmitted.

          The use of the partition circuit has two advantages: First, after dividing the LED large screen into sixteen partitions, the data transmission rate is reduced to one-sixteenth of the original to facilitate data transmission; second, the afterglow time of the LED is short. The screen refresh rate is required to be high. If the whole frequency is refreshed, it takes a long time to generate a flicker phenomenon. After the partition circuit is used, sixteen partitions are simultaneously refreshed, thus overcoming the screen flicker without increasing the complexity of the hardware. phenomenon.

          Third, the drive circuit

          The data outputted by the conversion circuit enters the LED driver circuit board, and the image data must be accurately transmitted and distributed to the corresponding LED dot matrix pixels. The system uses dynamic progressive scan mode to drive the LED display. Because the data of each partition is transmitted at the same time, the data transmission allocation and LED driving of each partition are consistent. In this system, the LED module used is an 8?—8dot line common anode and column common cathode module, which adopts a line common anode driving mode, that is, an image data input cathode, and a high level driving LED display is applied at a common anode. The input of the image data is through the eight-bit shift register 595, and each 595 chip corresponds to one LED module. At the beginning of a field, first, the shift signal controls the first line of data input, and when one row of data is all shifted into, one appears. The latch signal is outputted to the LED module. At the same time, the first row of the common anode inputs a high level to illuminate the first line; during the first line of illumination, the second line of data is simultaneously shifted, and the second After all the rows are shifted in, a latch pulse appears again. At the same time, the first row of the common anode disappears. The second row inputs the high level to the anode, and drives the second line to display. The first line is extinguished. While lighting the previous line, shift the input of the second line of data to keep the picture continuous.

          The above three parts of the hardware realize the synchronous display of the VGA video and the LED display, so that the LED large screen tracks the VGA video display.

          Fourth, the conclusion

          The information display of the system is not affected by the environment, and high-brightness display can be realized, and the system can select the screen size according to the requirements of the information display, thereby controlling the cost and having strong practicability, and has been applied in the comprehensive performance detection system of the automobile. Although this paper studies monochromatic systems, this method can also be extended to full-color display systems.

          亚洲 欧美 图片 自拍 视频
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