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          Design of Video Audio Monitoring System Based on DM642

          Abstract: In order to realize the real-time acquisition and transmission of video and audio data, a design scheme of video and audio monitoring system based on DM642 is proposed. On the hardware, the DM642's rich peripheral resources are used to complete the design of the video input and output modules, audio input and output modules and Ethernet interface modules. In software, based on DSP/BIOS real-time operating system, it realizes management and control of video and audio data, and builds a web server. Users can access the system through a browser to realize remote monitoring. The test results show that the system has stable performance and meets the design requirements.
          Keywords: DM642; video and audio monitoring; Ethernet; DSP/BIOS

          With the development of technology, the application field of video and audio monitoring systems is becoming wider and wider. At present, traditional video and audio monitoring systems have many disadvantages such as large size, small capacity, poor real-time performance, and low stability. The application is extremely inconvenient in industrial or military complex environments, and the application is greatly limited. TI's TMS320DM642 is a high-performance DSP chip for digital video applications with a 10/100 Mb/s Ethernet interface. Based on DM642, this paper presents a design scheme of video and audio monitoring system with local and remote video and audio monitoring capabilities. The design has the advantages of small size, low cost, high reliability, convenient use, etc., and has high research value and wide application prospect.

          1 Hardware Design According to the design requirements, this paper proposes a structural design based on TMS320DM642: including video input and output modules, audio input and output modules, and network interface modules. The overall structure is shown in Figure 1.

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          The main processor DM642 is a 32-bit fixed-point high-performance DSP from TI. It has rich video and audio hardware resources on the chip. It has various interfaces such as network port, PCI interface, I2C interface and serial port. It can be widely used. Video, audio, network, signal processing and other fields. The DM642 has a clock speed of 720 MHz and can execute 5 760 MIPS per second. Its EMIFA interface data bus width is 64 bits, the highest data access frequency is 133 MHz, and it can be directly connected to asynchronous registers and synchronous registers.
          When the DM642 expands the memory through the EMIFA interface, the CE0-CE3 signal is used as the spatial chip select signal. The DM642 externally expands two MT48LC2M32 chips, which have a total of 4M?—64-bit SDRAM space. The CE0 pin is used as the chip select signal, and the external memory area address range is 0x80000000~0x8007FFFF as the data buffer space. The external expansion is 1M?—8-bit FLASH, and the CE1 pin is used as the chip select signal. The external memory address range is 0x90000000~0x9001FFFF, which is used as the program storage space.
          1.1 Video Input and Output Module Design The DM642 integrates three independently configurable video ports VP0 to VP2, which are ideal for image processing systems. In this design, the VP0 port of the DM642 is configured as a video input mode, and the VP2 port is configured as a video output mode. The hardware circuit is shown in Figure 2.

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          The video decoder uses the SAF7113H from PHILIPS. The SAF7113H is a low-voltage, low-power, small-volume video decoder chip that supports NTSC, PAL, and SECAM video inputs with an output of 8 b ITU-RBT. 656 YCrCb 4:2:2 video data stream. The SAF7113H can be configured with an internal register via the I2C interface. The default read/write address is 4BH/4AH. When the pin HRTSO is grounded, the read/write address is 49H/48H.
          The video encoding chip adopts ADV7179 and supports NTSC and PAL video encoding. The DM642 configures the internal chip of the encoding chip ADV7179 through the I2C interface. The device address of the ADV7179 is determined by the state of the ALSB pin. In this design, ALSB is low and the read/write address is 55H/54H.
          1.2 Audio Input and Output Module Design The DM642's McASP interface can be used for multi-channel audio processing to receive and transmit audio data. The audio codec uses TI's TLC320AIC23B, a high-performance, low-power, two-channel stereo audio codec chip that integrates A/D decoding circuitry and D/A based on Sigma-del-ta sampling technology. Encoding circuit, support microphone input, stereo input and stereo output, programmable input and output gain, with headphone power amplifier on chip. The circuit connection between the DM642 and the AIC23B chip is shown in Figure 3.

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          The control port of the AIC23B chip supports the SPI protocol and the I2C protocol. The selection of the two types of interfaces is determined by the pin MODE state. In this design, the pin MODE is grounded, and the DM642 performs parameter configuration on the audio codec TLC320AIC23B through the I2C interface. The I2C device address of the TLC320AIC23B chip is selected by the pin CS. When the pin CS is grounded, the device address of the TLC320AIC23B is 0011010. The I2C bus selects the addressing mode of the 7-bit address. Since the registers of the AIC23B have only write operations and no read operations, the first 7 bits of each word of the I2C communication protocol are register addresses, and the last 9 bits are register contents.
          1.3 Design of the network interface module The DM642 has an EMAC interface and is compliant with the IEEE 802.3 protocol. It has 8 independent transmit and receive channels and supports 10 Mb/s or 100 Mb/s mode. In this design, an Ethernet transceiver LXT971A specially developed by Intel Corporation is adopted. The LXT971A uses an advanced CMOS process that requires only a single 3.3 V supply and its MII interface (independent multimedia interface) can be directly connected to the EMAC interface of the DM642. The LXT97IA's 4-way signal TD+, TD-, RD+, RD- is converted to a RJ 45 connector after being converted by a network transformer. The module structure is shown in Figure 4.

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          2 Software Design TI has developed a feature-rich, user-customizable real-time multitasking operating system DSP/BIOS for the TMS320C6000 series DSP, and provides a network tool development kit NDK. The toolkit provides HTTP services for fast development of network applications. The solution. DSP/BIOS provides a rich set of kernel services that allow users to quickly build multi-tasking applications with high real-time requirements and sophisticated complexity using DSP/BIOS.
          The software of this design is written in the integrated development environment CCS (C6000), using the algorithm provided by TI to process the data, realize the management and control of audio and video data, and build the Web server inside the DSP. The user is on the PC side. Remote monitoring is possible by accessing the system through a browser.
          Since DSP/BIOS is a multi-tasking operating system, the processing of the entire system is divided into three parts: audio acquisition and processing tasks, video acquisition and processing tasks, and HTTP service tasks. The overall process of the software is shown in Figure 5.

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          After the system is powered on, the bootloader is loaded from the FLASH, the initialization of the DM642 is completed, and the parameters of the video decoding chip SAF7113, the encoding chip ADV7179, and the audio codec AIC23B are configured. After the DSP/BIOS is started, the network tool development kit NDK is loaded in the main thread, and the system IP address, subnet mask, and default gateway are configured, and then the audio, video acquisition, and processing tasks are dynamically created, and the HTTP service is enabled.

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          The processing flow of the web server is shown in Figure 6. The system webpage design adopts the HTML language, and the homepage is loaded into the RAM when the system is started. The user inputs the system IP address through the browser on the PC side, and the web server returns to the main interface of the system. The data interaction between the web page and the server is in the form of a form. The CGI processing program extracts the useful information in the form, realizes the configuration of the system IP information, the parameter configuration of the video audio codec chip, and the real-time encoding of the video and audio. The data is transmitted to the user's browser in the form of a form to implement remote monitoring of the system.

          3 System Test In the integrated development environment CCS (C6000), the relevant driver was loaded and the system was tested. The CCD camera is a standard PAL system, the frame rate of image acquisition is 25 frames/s, and the resolution of the image is 720?—576 pixels. The test results are shown in Figure 7. The test results show that the network connection is normal, and the user can access the system through the browser on the PC side, and successfully realize remote monitoring.

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          4 Conclusion Based on DM642, a practical video and audio monitoring system is designed to realize real-time collection and transmission of video and audio data, which can be applied to remote monitoring, voice recognition, video telephony, digital television and other related fields. The test results show that the system has stable performance, high research value and wide application prospects.

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          亚洲 欧美 图片 自拍 视频
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